Changes between Version 2 and Version 3 of Internal/NoiseGenerator/Hardware/WiBo


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Timestamp:
Jan 13, 2007, 11:28:56 PM (18 years ago)
Author:
anonymous
Comment:

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  • Internal/NoiseGenerator/Hardware/WiBo

    v2 v3  
    1515
    1616The next copper layer down is all ground plane.  The third layer down is a signal layer with predominately vertical traces surrounded by ground plane.  The fourth or bottom layer is another signal layer with predominately horizontal traces.
     17
     18BiBo’s ADC (analog-to-digital conversion) and DAC (digital-to-analog) conversion comes from an Analog Devices AD9860 MxFE processor.  Digital RADIO_IO_x signals come from a Xilinx Spartan 3.
     19
     20RADIO_IO_1/3/4 download programming coefficients to the MAX2829.
     21
     22RADIO_IO_3/4 are shared with U2 (74HC595), an 8bit serial in parallel out shift register.  http://www.fairchildsemi.com/ds/MM/MM74HC595.pdf
     23U2 in turn controls five functions, namely, turn on/off of the 2GHz and 5GHz power amps, MAX2829 RXENA and TXENA signals and the MAX2829 shutdown (/SHDN). Meaning of control signals
     24
     25Assuming the MAX2829 has already been programmed, to enable a TX RF output the user must program a 11001xxx into U2. 
     26
     27NOTE! Do not turn on both the 2GHz and the 5GHz power amps at the same time!  ALSO! Do not turn on both the RXENA and TXENA lines (not sure why?).
     28
     29== Connector J3_F and I/O ==
     30 
     31This is a 40-pin 2mm dual-inline connector which mates BiBo’s control signals, +3.3 VDC power and ground to WiBo102.
     32
     33||WiBo102 function||J3_F function||pin#||pin#||J3_F function||WiBo102 function||                                               
     34||hi-speed MAX2829 TXBBQ-||DACB-||2||1||3.3VA|| ||
     35||hi-speed MAX2829 TXBBQ+||DACB+||4||3||GND|| ||
     36||hi-speed MAX2829 TXBBI-||DACA+||6||5||3.3VA|| ||
     37||hi-speed MAX2829 TXBBI+||DACA-||8||7||GND|| ||
     38||phase modulation of U23||AUX_DAC_C||10||9||3.3VA|| ||
     39||ref osc VCXO frequency adjust||AUX_DAC_B||12||11||GND|| ||
     40||PLL speed up monitor||AUX_DAC_A||14||13||3.3VA|| ||                                   
     41||1/2 supply voltage||AUX_ADC_A1||1||15 ||GND|| ||
     42||RSSI from MAX2829||AUX_ADC_A2 ||18||17||N/C|| ||
     43||2GHz power amp detector||AUX_ADC_B1||20||19||3.3VD|| ||       
     44||5GHz power amp detector||AUX_ADC_B2||22||21||GND|| ||                                                 
     45||hi-speed MAX2829 RXI+||ADCA+||24||23||3.3VD|| ||     
     46||hi-speed MAX2829 RXI-||ADCA_||26||25||GND|| ||       
     47||hi-speed MAX2829 RXQ+||ADCB+||28||27||3.3VD|| ||     
     48||hi-speed MAX2829 RXQ-||ADCB-||30||29||GND|| ||                                                       
     49||MAX2829 /CS||RADIO_IO 1||32||31||3.3VD|| ||   
     50||U2 RCK||RADIO_IO 2||34||33||GND|| || 
     51||MAX2829 SCLK and U2 SCK||RADIO_IO 3||36||35||RADIO_IO 8||MAX2829 LD (lock=1=LED on)||
     52||MAX2829 DIN and U2 SER||RADIO_IO 4||38||37||RADIO_IO 7||U5 switch(straight=0,cross=1)||
     53||U3 switch(straight=0,cross=1)||RADIO_IO 5||40||39||RADIO_IO 6||U4 switch(straight=0,cross=1)||
     54
     55=== Control Register U2 ===
     56                       
     57Note: A is the first bit in, so shift in reverse order         
     58               
     59||012345678||Function||
     60||1xxxxxxxx||turn MAX2829 on (/SHDN)||
     61||x1xxxxxxx||turn MAX2829 TX on (TXENA)||
     62||xx1xxxxxx||turn MAX2829 RX on (RXENA)||
     63||xxx1xxxxx||5G PA: 5GHZ power amp on||
     64||xxxx1xxxx||2G PA: 2GHz power amp on||
     65||xxxxx1xxx||SPARE 1 output on||
     66||xxxxxx1xx||SPARE 2 output on||
     67||xxxxxxx1x||SPARE 3 output on||
     68||xxxxxxxx1||SPARE 4 output on, 9th bit||
     69
     70