== Porting the RC5 Encryption Scheme to Synthesizable Verilog == 

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=== Mission  ===
The RC5 encryption scheme (Rivest's Cypher) will be ported to an FPGA using synthesizable verilog. The benefit of this would be scalability of encryption. 



=== Background  ===
==== Rivest's Cypher Encryption ====


=== Project Github  ===




=== Progress ===
 


=== Presentations  ===
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<a href = ""> Week 3 </a>
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=== The Team ===

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    <td><center><img src="http://www.orbit-lab.org/raw-attachment/wiki/Other/Summer/2016/SDRSpectrumDrone/nick.jpg" height=300></center></td>
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    <td align='center'><b>Nicholas Lurski</b><br>Electrical and Computer Engineering<br><br><i>Rutgers University</i></td>
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<br><br>Project guided by Dr. Richard Martin.

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