wiki:Hardware/bDomains/cSandboxes/fSB6

Version 15 (modified by seskar, 12 years ago) ( diff )

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SB6

Table of Contents

  1. Hardware
    1. Domains
      1. Sandboxes
        1. SB1
          1. RF Connections
        1. SB2
          1. RF Connections
          2. Networking Setup (eth2)
          3. Using images based on baselines before June 12, 2017
          4. Resetting / Rebooting X310's
        1. SB3
        1. SB4
          1. Node to Node RF Path
          2. Node to WiMAX basestation RF Path
        1. SB5
        1. SB6
          1. CR-Kit
          2. Parallela Platform
          3. WARP
        1. SB7
        1. SB8
        1. SB9
          1. Data Switch Connections
          2. Procedures (Edge Core Wedge)

Sanbox 6 (SB6) is dedicated to experimenting with variety of Software Defined Radio (SDR) platforms. Currently it has three different platforms as shown in diagram below:

SB6 Block Diagram SB6 Photo
CR-Kit

​GENI Cognitive Radio (CRKit) platform. Each of the two nodes, in addition to standard WiFi (Intel 2915) and WiMAX (Intel 6250) card, has ​CRKit with ​SDR device attached through dedicated Ethernet interface (eth2). The CRKIT is also connected to a host machine (node) via a JTAG to USB interface. This interface is used by software in the Xilinx SDK (Impact and Xilinx Bash Shell) to program the Virtex-5 FPGA. After all the programming has been performed over JTAG, the on board Ethernet controller takes over and communication between the node and the CRKit takes place via the Gigabit Ethernet interface with UDP packets.More details on the protocol are available at ​http://crkit.orbit-lab.org ; Basic tutorial is available at Tutorials/CRKit

Parallela Platform

The Parallela SDR platform is a software defined radio platform based on a 16-core Epiphany processor chip developed by ​Adapteva. The Epiphany multi-core chip daughter card is hosted by the ​Zedboard motherboard, as shown below:

Paralella Platfrom Block Diagram Parallela Kit Photo

GNU radio software can be executed within the Epiphany supercomputer, whereas control and IO related traffic is handled by the Zedboard Zynq dual-core ARM processor. The Zynq programmable logic section enables interfacing between the GNU Radio software and the lower level radio interfaces such as USRP.

WARP

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