wiki:Other/Summer/2017/FPGAEncryption

Version 4 (modified by nlurski, 7 years ago) ( diff )

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Porting the RC5 Encryption Scheme to Synthesizable Verilog

Table of Contents

  1. 2017 WINLAB Summer Internship
    1. Projects
  2. Drone Communication Analysis
    1. Introduction
    2. Background
    3. Tools Used
    4. Presentations
    5. Team Members
    1. Porting the RC5 Encryption Scheme to Synthesizable Verilog
      1. Mission
      2. Background
        1. Rivest's Cypher Encryption
      3. Progress
      4. Presentations
      5. The Team
  4. Mobility First : Multihoming Extension
    1. Introduction
      1. Mobility First
      2. Multihoming
    2. Mission
    3. Implementation
    4. Results
    5. Presentations
    6. People
  5. External References
    1. Quit Smoking Application
  7. SDR Smart Modem
    1. Introduction
    2. Background
    3. Tools Used
    4. Presentations
    5. The Team
    6. References

Mission

The RC5 encryption scheme (Rivest's Cypher) will be ported to an FPGA using synthesizable verilog. The benefit of this would be scalability of encryption.

Background

Rivest's Cypher Encryption

Progress

Presentations

Week 1

Week 2

Week 3

Week 4

Week 5

Week 7

Week 8

Week 9

The Team
Nicholas Lurski
Electrical and Computer Engineering

Rutgers University


Project guided by Dr. Richard Martin.

Attachments (10)

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